Trade-off and Design optimization of the Notch filter for ultralow power ECG application

ECG acquisition, several leads combined with signals from different body parts (i.e., from the right wrist and the left ankle) are utilized to trace the electric activity of the heart. ECG acquisition board translates the body signal to six leads and processes the signal using a low-pass filter (LPF) and SAR ADC. The acquisition board is composed of: an instrumentation amplifier, a high-pass filter, a 60-Hz notch filter, and a common-level adjuster. But miniaturization or need of portable devices for measuring Bio-Potential parameters has led to design of IC’s for biomedical application with ultra-low power Because of miniaturization i.e. use of lower technology nodes has led to non-idealities which reduces the attenuation of Common Mode to differential component i.e. not CMRR. Because of this demerit the power line interference signal can’t be assumed as a common mode signal. Hence we need to design a power line interference filter to avoid the contamination of the signal

A new offset cancellation technique for temperature sensors & Design of 8-bit decimation filter for biomedical applications

In our day to day life there are lot of things which we need to sense and then decide the course of action according to it. Many of these can be physically sensed easily, but the exact value of the sensed cannot be determined by human. There will be a lot of error in judged value and exact value. So instead of human sensing them and judging the exact value there are physical instruments which can provide lot more accurate value of sensed item than human, which are called SENSORS. There are lot of different sensors for sensing different things and one of prominent one is temperature sensor. Temperature sensor plays an important role in many applications. For example, maintaining a specific temperature is essential for equipment used to fabricate medical drugs, heat liquids or clean other equipment. For application like these, the accuracy of detection can be critical. The work done in this Thesis shows how to maintain the accuracy of temperature sensor. Temperature sensor used here is a Wheatstone bridge circuit consisting of two resistors and two thermistors. Mismatch between the resistors or thermistors will lead to incorrect detection of value, which is called OFFSET, therefore to maintain the accuracy the mismatch has to be minimized or removed. One of the Technique to minimize the offset and results pertaining to it has been displayed in this Thesis. Technique described in this Thesis consist of first sensing the difference between resistors value, one being the reference resistor and other the on-chip resistor used in temperature sensing, second amplifying the difference of resistor value using OPAMP, third sending the amplified signal to single ended SAR ADC, which gives digital bits as output. And according to the digital output changing resistor value using resistor switching method. Thus then this resistor will be used in wheat stone bridge temperature sensing. The work proposed here can increase or decrease on-chip resistor value depending on reference resistor. The wheat stone bridge Resistor can be changed by plus minus 5K ohms with respect to reference resistor. This is a onetime calibration technique used before start of sensing temperature. After the resistor have been calibrated, these resistors are used in wheat stone bridge along with thermistor to sense temperature and the differential output obtained through wheat stone is passed on to the dual ended SAR ADC, which gives digital representation of temperature sensed

A Stage-Stage Dead-Band Compensated Multiband RF Energy Harvester for Sensor Nodes

This article presents a dead-band compensated multiband stacked electromagnetic energy harvester for powering sensor nodes. It is adaptive for typical ambient radio frequency (RF) power levels found within the environment. A stage-stage feedforward technique is adopted in the proposed harvester to enhance the output voltage, in turn, harvested power and sensitivity. Moreover, a compensation circuit is included in the design for bypassing the inactive bands to avoid unexcited band rectifier diodes. A prototype is designed to cover four frequency bands GSM (900 and 1800 MHz), 4G-LTE (2.3 GHz), and Wi-Fi (2.4 GHz) and further integrated with a TI BQ25570 power converter. The analytical, simulated, and measured results show the increment in the output voltage with the frequency bands. The measured efficiency of the RF-to-dc converter is 44.2% at -20-dBm input power and 89% at 0 dBm. The efficiency is improved by 13% on average under dead-band compensation. With the multiband stacking, the harvester achieves a start-up voltage of 320 mV at -24 dBm and is found to be efficient to drive a temperature sensor STLM20 at -12-dBm input power

Capacitance-to-Digital Converter for Ultra-Low-Power Wireless Sensor Nodes

Power consumption is one of the main design constraints in today’s integrated circuits. For systems like wearable electronics, UAVs, IOT systems powered by batteries which are charged using the energy harvested from various sources like RF, Thermal, Solar and Vibration, ultra-low power consumption is paramount. In these systems, Transducers which convert physical parameters into electrical parameters and the analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power signal Front End used in several low power electronic systems in general and pressure measurement systems in particular. In this thesis, Capacitance to Digital Converter based pressure measurement system has been implemented. Here we present a general-purpose, wide-range CDC that combines a correlated double sampling (CDS) approach with a differential asynchronous SAR ADC. Since the sensor capacitor is sampled only twice per conversion, energy per conversion is low. Furthermore, since the CDS separates the sensor capacitor from the CDAC, a full differential input voltage range is preserved. The CDC has a 2.5-to-75.5pF conversion range. Monotonic SAR ADC was designed in 180nm CMOS with 1-V power supply and a 1-kS/s sampling rate with switching energy of about 100nW

An enhanced recycling folded cascade OTA with a positive feedback

In this paper an enhanced fully differential recycling folded cascode operational trans conductance amplifier that achieves higher DC gain with same power and area as that of recycling folded cascode OTA is discussed. Generally, the output impedance of the cascode amplifier depends on the current flowing into the cascode node. Hence, in order to increase the DC gain of the conventional Recycling Folded Cascode OTA the modification is done at the cascode node. The proposed enhanced fully differential RFC OTA is implemented in strong inversion using gm/Id methodology. The design is carried out using UMC180nm technology and studied through simulation. From simulation, we found an increase in DC gain of 9dB, 14dB, and 24dB is achieved without changing the Unity Gain Bandwidth

Analysis of Impact of Transformer Coupled Input Matching on Concurrent Dual-Band Low Noise Amplifier

Emerging advancements in telecommunication system need robust radio devices which can capable of working multiple frequency bands seamlessly. In any Radio Frequency (RF) receiver architecture, Low Noise Amplifier (LNA) is the mandatory front-end part in which takes place in between antenna and mixer. To support multiple frequency bands with single hardware, concurrent LNA is the more preferred topologies among others. As LNA is the very front end level of receiver, Input matching, Noise Figure (NF) and gain are the major performance parameters to be concerned. In this work, the impact of transformer coupled input matching on concurrent dual-band LNA is analyzed and verified. A concurrent LNA with concurrent matching without transformer coupling is used for comparison. A transformer coupled input matching is proposed for tunable concurrent dual-band LNA. All the circuits are implemented in UMC 180nm CMOS technology, and simulated using Cadence SpectreRF simulation tool

Design and Analysis of Charge Pump and Loop Filter for Wideband PLL

The growing market for wireless applications demands low-cost low-power system-on-chip (SOC) transceiver systems. The frequency synthesizer, used as local oscillator, is one of the most critical building blocks in any integrated transceiver sys-tem. As the demand of low-power low-voltage cost-effective high frequency system increases, design is getting more and more challenging. Due to the high level of integration, digital CMOS process is most favorable for SOC design but it increases the design challenges for RF circuits. This research work is carried out on the design and implementation of low-power low-noise low-cost frequency synthesizer in 0.18μmepi-digital CMOS process. A new scheme has been used to linearize the VCO output frequency versus tuning voltage characteristic, which reduces the VCO gain. Jitter modeling in cadence has been discussed

Efficient adaptive switch design for charge pumps in micro-scale energy harvesting

The performance of Micro-scale energy harvesting unit depends on the efficient design of charge-pump. Optimization of the dimension of MOSFET switches in charge pump is one of the techniques to improve the efficiency. In this work, a new optimization technique for transistor sizing and a concept of reconfigurable adaptive switches has been introduced to maximize the extracted power. A control unit is designed for adaptive reconfiguration of the switches. These proposed techniques are validated for linear charge-pump topology in UMC 180nm technology. Combined effect of size optimization of switch along with reconfigurable switch offers an improvement up to 23.5% in the net harvested power with 6% less silicon area

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

A True 1V 1µW Biomedical Front End with Reconfigurable ADC for Self powered Smarter IoT Healthcare Systems

This work proposes an ultralow power highly linear analog front-end (AFE) with an input dynamic range from 200μVpp to 20mVpp. The system consists of a signal conditioning instrumentation amplifier (IA), two programmable gain amplifiers (PGA), a mixed signal automatic gain control (AGC), two sample and hold (S/H), a 10 bit successive approximation register (SAR) analog to digital converter (ADC), and a ΣΔ modulator with 10 bit effective number of bits (ENOB). A highly linear capacitively-coupled IA is achieved by increasing its feedback factor. Moreover, a transconductance (gm) cancellation technique is proposed for achieving a high common mode rejection ratio (CMRR). The conditioned signal is digitized using a SAR ADC for an input range of 200μVpp to 2mVpp, and, an opamp-shared ΣΔ ADC for an input range of 2mVpp to 20mVpp. The selection between the two ADCs is done by the AGC. The full system is designed using 1V supply in UMC 0.18μm CMOS technology. The AFE (IA and the two PGAs) achieves an overall linearity of more than 12 bits, for an input range of 200μVpp to 20mVpp while consuming 300nW with a bandwidth of 0.05 - 250Hz. The power consumption of the SAR ADC is 40nW while operating at a sampling frequency of 1KHz. The ΣΔ ADC consumes 300nW at a sampling frequency of 32KHz with an OSR of 32. The proposed system is intended to be powered by an energy scavenging circuit without compromising its own performance. The system was successfully tested for an ECG signal obtained from PTB database